1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit device, and more particularly, to a multifunctional semiconductor integrated circuit device comprising a non-reprogrammable internal memory device.
2. Description of the Background Art
FIG. 4 is a connection diagram in the trial manufacture and evaluation of a system comprising a conventional IC memory and a CPU (Central Processing Unit).
In FIG. 4, an IC memory 10 comprises a ROM (Read Only Memory) in which the pattern of stored data cannot be changed. At the time of trial manufacture and evaluation of a system comprising such an IC memory 10 and a CPU 20, operation tests of the IC memory 10 and the CPU 20 must be performed while changing the pattern of data stored in the ROM. Therefore, in many cases, evaluation is performed with an EPROM (Erasable Programmable Read Only Memory) 30 in which the pattern of stored data can be changed being externally connected to the ROM portion.
In FIG. 4, the IC memory 10 comprises a ROM in which the pattern of stored data cannot be changed, such as a mask ROM and an OTPROM (One Time Programmable Read Only Memory) formed by sealing in a plastic package an EPROM chip capable of erasure by ultraviolet rays. A multiplex pin AD/DA of the CPU 20 is used for outputting an address signal and inputting data. The address signal outputted from the multiplex pin AD/DA is applied to a latch circuit 40. This address signal is stationarily applied to respective address pins AD of the IC memory 10 and the EPROM 30 in response to a timing signal from an address latch enable pin ALE of the CPU 20. Respective data pins DA of the IC memory 10 and the EPROM 30 are directly connected to the multiplex pin AD/DA of the CPU 20. An output of a decoder circuit 50 is applied to respective chip enable pins CE of the IC memory 10 and the EPROM 30.
Each of the IC memory 10 and the EPROM 30 is rendered active only when a signal applied to the chip enable pin CE thereof is at the "L" level. Thus, when the externally connected EPROM 30 is used, "L" and "H" level signals are respectively applied to the chip enable pins CE of the EPROM 30 and the IC memory 10 by the decoder circuit 50. Consequently, an output of the data pin DA of the IC memory 10 becomes the floating level, not to conflict with data from the data pin DA of the EPROM 30.
Meanwhile, the connection diagram of FIG. 4 is typically drawn. In practice, there exist a plurality of multiplex pins AD/DA, and a control signal outputted from the CPU 20 becomes more complicated depending on the system.
As described in the foregoing, in a ROM in which the pattern of stored data cannot be changed and a conventional IC memory comprising such a ROM, additional circuits such as a decoder circuit and a latch circuit are required in using an externally connected EPROM for trial manufacture and evaluation.